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a
FEATURES 140 MSPS Guaranteed Conversion Rate 100 MSPS Low Cost Version Available 330 MHz Analog Bandwidth 1 V p-p Analog Input Range Internal +2.5 V Reference Differential or Single-Ended Clock Input 3.3 V/5.0 V Three-State CMOS Outputs Single or Demultiplexed Output Ports Data Clock Output Provided Low Power: 1.0 W Typical +5 V Converter Power Supply APPLICATIONS RGB Graphics Processing High Resolution Video LCD Monitors and Projectors Micromirror Projectors Plasma Display Panels Scan Converters
R AIN R AIN G AIN G AIN B AIN B AIN ENCODE ENCODE DS DS
Triple 8-Bit, 140 MSPS A/D Converter AD9483
FUNCTIONAL BLOCK DIAGRAM
AD9483
T/H QUANTIZER 8 DRA7-0 DRB7-0 T/H QUANTIZER 8 DGA7-0 DGB7-0 T/H QUANTIZER 8 DBA7-0 DBB7-0
TIMING
CLKOUT CLKOUT OMS I/P PD
CONTROL +2.5V
VREF RVREF GVREF BVREF VCC VDD GND OUT IN IN IN
GENERAL DESCRIPTION
The AD9483 is a triple 8-bit monolithic analog-to-digital converter optimized for digitizing RGB graphics signals from personal computers and workstations. Its 140 MSPS encode rate capability and full-power analog bandwidth of 330 MHz supports display resolutions of up to 1280 x 1024 at 75 Hz with sufficient input bandwidth to accurately acquire and digitize each pixel. To minimize system cost and power dissipation, the AD9483 includes an internal +2.5 V reference and track-and-hold circuit. The user provides only a +5 V power supply and an encode clock. No external reference or driver components are required for many applications. The digital outputs are threestate CMOS outputs. Separate output power supply pins support interfacing with 3.3 V or 5 V logic. The AD9483's encode input interfaces directly to TTL, CMOS, or positive-ECL logic and will operate with single-ended or differential inputs. The user may select dual channel or single channel digital outputs. The Dual Channel (demultiplexed)
mode interleaves ADC data through two 8-bit channels at onehalf the clock rate. Operation in Dual Channel mode reduces the speed and cost of external digital interfaces while allowing the ADCs to be clocked to the full 140 MSPS conversion rate. In the Single Channel mode, all data is piped at the full clock rate to the Channel A outputs and the ADCs conversion rate is limited to 100 MSPS. A data clock output is provided at the Channel A output data rate for both Dual-Channel or SingleChannel output modes. Fabricated in an advanced BiCMOS process, the AD9483 is provided in a space-saving 100-lead MQFP surface mount plastic package (S-100) and is specified over the 0C to +85C temperature range.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
AD9483-SPECIFICATIONS differential PECL)
Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes Gain Error1 Gain Tempco1 ANALOG INPUT Input Voltage Range (With Respect to AIN) Compliance Range AIN or AIN Input Offset Voltage Input Resistance Input Capacitance Input Bias Current Analog Bandwidth, Full Power REFERENCE OUTPUT Output Voltage Temperature Coefficient SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Encode Pulsewidth High (tEH) Encode Pulsewidth Low (tEL) Aperture Delay (tA) Aperture Delay Matching Aperture Uncertainty (Jitter) Data Sync Setup Time (tSDS) Data Sync Hold Time (tHDS) Data Sync Pulsewidth (tPWDS) Output Valid Time (tV)2 Output Propagation Delay (tPD)2 Clock Valid Time (tCV)3 Clock Propagation Delay (tCPD)3 Data to Clock Skew (tV-tCV) Data to Clock Skew (tPD-tCPD) DIGITAL INPUTS Input Capacitance DIFFERENTIAL INPUTS Differential Signal Amplitude (VID) HIGH Input Voltage (VIHD) LOW Input Voltage (VILD) Common-Mode Input (VICM) HIGH Level Current (IIH) LOW Level Current (IIL) VREF IN Input Resistance +25C Full +25C Full Full +25C Full I VI I VI VI I V Temperature Test Level
(VCC = +5 V, VDD = +3.3 V, external reference, ENCODE = maximum conversion rate
AD9483KS-140 Typ Max 8 1.25/-1.0 1.50/-1.0 0.9 1.50/-1.50 1.75/-1.75 Guaranteed 1 2 160 0.8 AD9483KS-100 Min Typ Max 8 1.25/-1.0 1.50/-1.0 0.9 1.50/-1.50 1.75/-1.75 Guaranteed 1 2 160 0.8
Min
Units Bits LSB LSB LSB LSB % FS ppm/C
Full Full +25C Full +25C Full +25C +25C Full +25C Full Full Full Full +25C +25C +25C +25C +25C +25C +25C +25C Full Full Full Full Full Full +25C Full Full Full Full Full Full +25C
V V I VI I VI V I VI V VI V VI IV IV IV V V V IV IV IV VI VI VI VI VI VI V IV IV IV IV VI VI V
512 1.8 4 83 4 17 330 +2.4 +2.5 110 140 2.8 2.8 1.5 100 2.3 0 0.5 2.0 4.0 3.8 -1.0 -2.0 0 0.5 2.0 4.0 10 3.8 10 1.0 2.0 -1.0 -2.0 10 50 50 +2.6 +2.4 3.2 16 20 1.8
512 4 83 4 17 330 +2.5 110 +2.6 3.2 16 20
35 25
35 25 36 50
36 50
mV p-p V mV mV k k pF A A MHz V ppm/C MSPS MSPS ns ns ns ps ps rms ns ns ns ns ns ns ns ns ns pF mV V V V mA mA k
100 4.0 4.0 1.5 100 2.3 10 50 50
6.3 8.0 6.2 8.0 0 0 3
6.3 8.0 6.2 8.0 0 0 3
10 10 1.0 2.0
400 0.4 0 1.5
VCC 1.2 1.2 2.5
400 0.4 0 1.5
VCC 1.2 1.2 2.5
-2-
REV. A
AD9483
Parameter SINGLE-ENDED INPUTS HIGH Input Voltage (VIH) LOW Input Voltage (VIL) HIGH Level Current (IIH) LOW Level Current (IIL) DIGITAL OUTPUTS Logic "1" Voltage Logic "0" Voltage Output Coding POWER SUPPLY VCC Supply Current VDD Supply Current Total Power Dissipation4 Power-Down Supply Current Power-Down Dissipation DYNAMIC PERFORMANCE5 Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 19.7 MHz fIN = 49.7 MHz fIN = 69.7 MHz Signal-to-Noise Ratio (SINAD) (With Harmonics) fIN = 19.7 MHz fIN = 49.7 MHz fIN = 69.7 MHz Effective Number of Bits fIN = 19.7 MHz fIN = 49.7 MHz fIN = 69.7 MHz 2nd Harmonic Distortion fIN = 19.7 MHz fIN = 49.7 MHz fIN = 69.7 MHz 3rd Harmonic Distortion fIN = 19.7 MHz fIN = 49.7 MHz fIN = 69.7 MHz Crosstalk Temperature Full Full Full Full Full Full Test Level IV IV VI VI VI VI Min 2.0 0 AD9483KS-140 Typ Max VCC 0.8 1 1 AD9483KS-100 Min Typ Max 2.0 0 VCC 0.8 1 1 Units V V mA mA V V
VDD - 0.05 0.05 Binary
VDD - 0.05 0.05 Binary 215 60 1.3 20 100 215 60 1.3 20 100
Full Full Full +25C +25C +25C +25C
VI VI VI V V V V
1.0 4 20 1.5 1.5
1.0 4 20 1.5 1.5
mA mA W mA mW ns ns
+25C +25C +25C
V I V
41
45 44 44
41
45 44 44
dB dB dB
+25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C Full
V I V V I V V I V V I V V
40
44 43 42 7.0 6.8 6.8 63 58 51 56 54 51 55
40
44 43 42 7.0 6.8 6.8 63 58 51 56 54 51 55
dB dB dB Bits Bits Bits dBc dBc dBc dBc dBc dBc dB
6.4
6.4
50
50
46
46
NOTES 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference). 2 tV and t PDF are measured from the threshold crossing of the ENCODE input to valid TTL levels at the digital outputs. The output ac load during test is 5 pF. 3 tCV and tCPD are measured from the threshold crossing of the ENCODE input to valid TTL levels at the digital outputs. The output ac load during test is 20 pF. 4 Measured under the following conditions: analog input is -1 dBFS at 19.7 MHz. 5 SNR/harmonics based on an analog input voltage of -1.0 dBFS referenced to a 1.024 V full-scale input range. Typical thermal impedance for the S-100 (MQFP) 100-lead package: JC = 10C/W, CA = 17C/W, JA = 27C/W. Specifications subject to change without notice.
REV. A
-3-
AD9483
ABSOLUTE MAXIMUM RATINGS* Table I. Output Coding
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to 0.0 V VREF IN, VREF OUT . . . . . . . . . . . . . . . . . . . . VCC to 0.0 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to 0.0 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . . . . . 0C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . +175C Maximum Case Temperature . . . . . . . . . . . . . . . . . . . +150C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.
Step 255 254 253 * * * 129 128 127 126 * * * 2 1 0
AIN-AIN 0.512 V 0.508 V 0.504 V * * * 0.006 V 0.002 V -0.002 V -0.006 V * * * -0.504 V -0.508 V -0.512 V
Code 255 254 253 * * * 129 128 127 126 * * * 2 1 0
Binary 1111 1111 1111 1110 1111 1101 * * * 1000 0001 1000 0000 0111 1111 0111 1110 * * * 0000 0010 0000 0001 0000 0000
EXPLANATION OF TEST LEVELS
Test Level I - 100% production tested. II - 100% production tested at +25C and sample tested at specified temperatures. III - Periodically sample tested. IV - Parameter is guaranteed by design and characterization testing. V - Parameter is a typical value only. VI - 100% production tested at +25C; guaranteed by design and characterization testing.
ORDERING GUIDE
Model AD9483KS-100 AD9483KS-140 AD9483/PCB
Temperature Range 0C to +85C 0C to +85C +25C
Package Description Plastic Thin Quad Flatpack Plastic Thin Quad Flatpack Evaluation Board
Package Option S-100B S-100B
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9483 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. A
AD9483
PIN FUNCTION DESCRIPTIONS
Pin Number 1, 6, 7, 10, 20, 30, 40, 50, 60, 70, 73, 77, 78, 80, 81, 95, 96, 100 2 3 4 5 8 9 11, 21, 31, 41, 51, 61, 71 79, 82, 83, 93, 94, 98, 99 12-19 22-29 32-39 42-49 52-59 62-69 72 74 75 76 84 85 86 87 88 89 90 91 92 97
Name
Function
GND ENCODE ENCODE DS DS DCO DCO VDD VCC DBB7-DBB0 DBA7-DBA0 DGB7-DGB0 DGA7-DGA0 DRB7-DRB0 DRA7-DRA0 NC OMS I/P PD R AIN R AIN R REF IN G AIN G AIN G REF IN B AIN B AIN B REF IN REF OUT
Ground Encode clock for ADC (ADC samples on rising edge of ENCODE). Encode clock complement (ADC samples on falling edge of ENCODE). Data Sync Aligns output channels in Dual-Channel mode. Data Sync complement. Data Clock Output. Clock output at Channel A data rate. Data Clock Output complement. Output Power Supply. Nominally 3.3 V. Converter Power Supply. Nominally 5.0 V. Digital Outputs of Converter "B," Channel B. DBB7 is the MSB. Digital Outputs of Converter "B," Channel A. DBA7 is the MSB. Digital Outputs of Converter "G," Channel B. DGB7 is the MSB. Digital Outputs of Converter "G," Channel A. DGA7 is the MSB. Digital Outputs of Converter "R," Channel B. DRB7 is the MSB. Digital Outputs of Converter "R," Channel A. DRA7 is the MSB. No Connect. Selects Single Channel or Dual Channel output mode, (HIGH = single, LOW = demuxed). Selects interleaved or parallel output mode, (HIGH = interleaved, LOW = parallel). Power-Down and Three-State Select (HIGH = power-down). Analog Input Complement for Converter "R." Analog Input True for Converter "R." Reference Input for Converter "R" (+2.5 V Typical, 10%). Analog Input Complement for Converter "G." Analog Input True for Converter "G." Reference Input for Converter "G" (+2.5 V Typical, 10%). Analog Input Complement for Converter "B." Analog Input True for Converter "B." Reference Input for Converter "B" (+2.5 V Typical, 10%). Internal Reference Output (+2.5 V Typical); Bypass with 0.01 F to Ground.
REV. A
-5-
AD9483
PIN CONFIGURATION Plastic Thin Quad Flatpack (S-100B)
97 REF OUT
89 G REF IN
92 B REF IN
88 G AIN
87 G AIN
90 B AIN
86 R REF IN
91 B AIN
100 GND
84 R AIN
85 R AIN
98 VCC
95 GND
99 VCC
96 GND
GND ENCODE ENCODE DS DS GND GND DCO DCO
82 VCC
83 VCC
93 VCC
94 VCC
81 GND
1 2 3 4 5 6 7 8 9
PIN 1 IDENTIFIER
80 GND 79 VCC 78 GND 77 GND 76 PD 75 I/P 74 OMS 73 GND 72 NC 71 VDD 70 GND 69 DRA 0 68 DRA 1 67 DRA 2 66 DRA 3 65 DRA 4 64 DRA 5 63 DRA 6 62 DRA 7 61 VDD 60 GND 59 DRB 0 58 DRB 1 57 DRB 2 56 DRB 3 55 DRB 4 54 DRB 5 53 DRB 6 52 DRB 7 51 VDD
VDD 31 DGB7 32 DGB6 33 DGB2 37 DGB0 39 DGA4 45 DGA3 46 DGA0 49 DGB5 34 DGB4 35 DGA2 47 DGA1 48 DGB1 38 DGB3 36 DGA6 43 DGA5 44 DGA7 42 GND 50 GND 40 VDD 41
GND 10 VDD 11 D BB7 12 D BB6 13 D BB5 14 D BB4 15 D BB3 16 D BB2 17 D BB1 18 D BB0 19 GND 20 VDD 21 D BA 7 22 D BA 6 23 D BA 5 24 D BA 4 25 D BA 3 26 D BA 2 27 D BA 1 28 D BA 0 29 GND 30
AD9483
TOP VIEW (PINS DOWN)
NC = NO CONNECT
-6-
REV. A
AD9483
TIMING
SAMPLE N-1 AIN SAMPLE N SAMPLE N+3 SAMPLE N+4
tA
ENCODE ENCODE
SAMPLE N+1
SAMPLE N+2
t EH
t EL
1/f S
t PD
D7-D0 DATA N-5 DATA N-4 DATA N-3 DATA N-2 DATA N-1
tV
DATA N
t CPD
CLOCK OUT CLOCK OUT
t CV
Figure 1. Timing--Single Channel Mode
SAMPLE N-1 AIN SAMPLE N-2
SAMPLE N
SAMPLE N+3
SAMPLE N+4
SAMPLE N+5
t EH
ENCODE ENCODE
t EL
tA 1/f S
SAMPLE N+1
SAMPLE N+2
SAMPLE N+6
t HDS
DS DS
t SDS
t PD
INTERLEAVED DATA OUT
tV
PORT A D7-D0
DATA N-7 OR N-8
DATA N-7 OR N-6
INVALID IF OUT OF SYNC DATA N-4 IF IN SYNC
DATA N-2
DATA N
PORT B D7-D0
DATA N-8 OR N-7
DATA N-6 OR N-7
INVALID IF OUT OF SYNC DATA N-5 IF IN SYNC PARALLEL DATA OUT
DATA N-3
DATA N-1
DATA N+1
PORT A D7-D0
DATA N-9 OR N-8
DATA N-7 OR N-8
DATA N-7 OR N-6
INVALID IF OUT OF SYNC DATA N-4 IF IN SYNC
DATA N-2
DATA N
PORT B D7-D0
DATA N-8 OR N-7
DATA N-6 OR N-7
INVALID IF OUT OF SYNC DATA N-5 IF IN SYNC
DATA N-3
DATA N-1
DATA N+1
t CPD
CLKOUT CLKOUT
t CV
Figure 2. Timing--Dual Channel Mode
REV. A
-7-
AD9483
EQUIVALENT CIRCUITS
VCC VDD
AD9483
AIN AIN DIGITAL OUTPUTS
AD9483
Figure 3. Equivalent Analog Input Circuit
Figure 7. Equivalent Digital Output Circuit
VCC
VCC
VREF IN 500 VREF OUT
AD9483
2k
AD9483
Figure 4. Equivalent Reference Input Circuit
Figure 8. Equivalent Reference Output Circuit
VCC 17.5k ENCODE DS 300
VCC
AD9483
ENCODE DS
AD9483
300
7.5k
DIGITAL INPUTS
Figure 5. Equivalent Encode and Data Select Input Circuit
Figure 9. Equivalent Digital Input Circuit
VCC
AD9483
DEMUX
Figure 6. Equivalent DEMUX Input Circuit
-8-
REV. A
Typical Performance Characteristics-AD9483
0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 -5 0 50 100 150 200 250 300 350 400 450
2.4 -40 -20 0 20 40 60 TEMPERATURE - C 80 100 2.42 2.48 2.5
NYQUIST FREQUENCY (70MHz)
-3dB (333MHz)
2.46
VOLTS
2.44
dB
fIN - MHz
Figure 10. Frequency Response: fS = 140 MSPS
Figure 13. Reference Voltage vs. Temperature
-70 -60 -50
2.6
2.5
2.4
VREF
0 2.5 5 7.5 10 25 50 fIN - MHz 75 100 150 200 250
-40
dB
2.3
-30
2.2
-20 -10 0
2.1
2 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 6.2 6.4 VCC - V
Figure 11. Crosstalk vs. fIN: fS = 140 MSPS
Figure 14. Reference Voltage vs. Power Supply Voltage
-80
2.6 2.5
-75
2.4 2.3 2.2
-70 VOLTS 10 20 30 40 50 60 70 TEMPERATURE - C 80 90 100
dB
-65
2.1 2
-60
1.9 1.8 1.7
-55
-50 0
1.6 0 1 2 3 4 5 6 789 IREF - mA 10 11 12 13 14 15
Figure 12. Crosstalk vs. Temperature: fIN = 70 MHz
Figure 15. Reference Voltage vs. Reference Load
REV. A
-9-
AD9483-Typical Performance Characteristics
9 8.5 8 7.5 7
ns
5
TPD 3.3V
4.5 4
VDD = +5V
TPD 5V
VOLTS
3.5 3 2.5 2 VDD = +3.3V
TV 5V
6.5 6 5.5 5 4.5 4 5 10 15 20 LOAD CAPACITANCE - pF 25 30 TV 3.3V
1.5 1 0.5 0 0 2 4 6 8 12 10 IOH - mA 14 16 18 20
Figure 16. Clock Output Delay vs. Capacitance
Figure 19. Output Voltage HIGH vs. Output Current
9 8 7 6 TPD
2 1.8 1.6 1.4
TV
1.2
VOLTS
5
ns
1 0.8
4 3 2 1 0 3
0.6 0.4 VDD = +3.3V 0.2 0
3.3 3.6 3.9 4.2 4.5 VDD - V 4.75 5 5.25 5.5
VDD = +5V 0 5 10 IOL 15 20
Figure 17. Output Delay vs. VDD
Figure 20. Output Voltage LOW vs. Output Current
9 8.5 8 7.5 7 ns 6.5 6 TV 3.3V 5.5 5 4.5 4 -40 TV 5V TPD 5V TPD 3.3V
600
500
400
mW
300
200
100
0
0 50 TEMPERATURE - C
100
3
3.5
4 VDD - V
4.5
5
5.5
Figure 18. Output Delay vs Temperature
Figure 21. Output Power vs. VDD, CLOAD = 10 pF
-10-
REV. A
AD9483
50 48 46 SNR 44 42 dB 40 38 36 34 32 30 0 30 60 100 fS - MSPS 140 180 SINAD dB
50 48 46 44 42 40 38 36 34 32 30 0 20 40 60 80 100 120 fS - MSPS 140 160 180 200 SINAD SNR
Figure 22. SNR vs. fS: fIN = 19.7 MHz
Figure 25. SNR vs fS: fIN = 71.7 MHz
-75
-56 -54 2ND HARMONIC
-70 3RD HARMONIC -65 dB
dB
-52 -50 -48 3RD HARMONIC -46 -44
-60 2ND HARMONIC -55
-42 -40 -38
-50 0 25 50 90 fS - MSPS 130 170
-36 0 40 80 120 fS - MSPS 155 175
Figure 23. Harmonic Distortion vs. fS: fIN = 19.7 MHz
Figure 26. Harmonic Distortion vs fS: fIN = 71.7 MHz
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 0 10 20 30 40 50 MHz 60 70 80 90 100 FUNDAMENTAL = -0.5dBFS SNR = 45.8dB SINAD = 45.2dB 2ND HARMONIC = 69.8dB 3RD HARMONIC = 61.6dB
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 0 10 20 30 40 50 MHz 60 70 80 90 100 FUNDAMENTAL = -0.5dBFS SNR = 44.6dB SINAD = 37.6dB 2ND HARMONIC = 63.1dB 3RD HARMONIC = 39.1dB
dB
Figure 24. Spectrum: fS = 140 MSPS, fIN = 19.57 MHz
Figure 27. Spectrum: fS = 140 MSPS, fIN = 70.3 MHz
REV. A
-11-
dB
AD9483
46 44 42 40 fS = 140 MSPS fIN = 19.3MHz SNR
46 SNR 45
SINAD
44
SINAD
dB
dB
38 36
43
42
34 32 30 25% 28% 2 1.8 31% 2.2 38% 45% 52% 59% 66% 73% 76% 2.7 3.2 3.7 4.2 4.7 5.2 5.4 ENCODE DUTY CYCLE - % ENCODE PULSEWIDTH - ns
41
40 -25
0
40 60 TEMPERATURE - C
80
100
Figure 28. SNR vs. Clock Pulsewidth (tPWH): fS = 140 MSPS
Figure 31. SNR vs. Temperature, fS = 140 MSPS
55
-70
50 NYQUIST FREQUENCY (70.0MHz) 45 dB
dB
-65
-60
-55
SNR 40
-50
35
SINAD
-45
30
0
50
100
150 fIN - MHz
200
250
-40 -25
0
40 60 TEMPERATURE - C
80
100
Figure 29. SNR vs. fIN: fS = 140 MSPS
Figure 32. 2nd Harmonic vs. Temperature, fS = 140 MSPS
-60
0 -10 F1 = 55.0MHz F2 = 56.0MHz F1 = F2 = -7.0dBFS
-56
-20 -30
-52
-40
dB
dB
-48 -44 -40 -25
-50 -60 -70 -80 -90
-100
0
40 60 TEMPERATURE - C
80
100
0
10
20
30
40
50 MHz
60
70
80
90
100
Figure 30. 3rd Harmonic vs. Temperature, fS = 140 MSPS
Figure 33. Two Tone Intermodulation Distortion
-12-
REV. A
AD9483
APPLICATION NOTES Theory of Operation
The AD9483 combines Analog Devices' patented MagAmp bitper-stage architecture with flash converter technology to create a high performance, low power ADC. For ease of use the part includes an on board reference and input logic that accepts TTL, CMOS or PECL levels. Each of the three analog input signals is buffered by a high speed differential amplifier and applied to a track-and-hold (T/H) circuit. This T/H captures the value of the input at the sampling instant and maintains it for the duration of the conversion. The sampling and conversion process is initiated by a rising edge on the ENCODE input. Once the signal is captured by the T/H, the four Most Significant Bits (MSBs) are sequentially encoded by the MagAmp string. The residue signal is then encoded by a flash comparator string to generate the four Least Significant Bits (LSBs). The comparator outputs are decoded and combined into the 8-bit result. If the user has selected Single Channel mode (OMS = HIGH) the 8-bit data word is directed to an A output bank. Data are strobed to the output on the rising edge of the ENCODE input with four pipeline delays. If the user has selected Dual Channel mode (OMS = LOW) the data are alternately directed between the A and B output banks and the data has five pipeline delays. At power-up, the N sample data can appear at either the A or B Port. To align the data in a known state, the user must strobe DATA SYNC (DS, DS) per the conditions described in the Timing section.
Graphics Applications
needs to be driven, which in turn minimizes on-chip noise due to heavy current flow in the outputs. We have obtained optimum performance on our evaluation board by tying all VCC pins to a quiet analog power supply system and tying all GND pins to a quiet analog system ground.
Minimum Encode Rate
The minimum sampling rate for the AD9483 is 10 MHz for the 140 MSPS and 100 MSPS versions. To achieve this sampling rate, the Track/Hold circuit employs a very small hold capacitor. When operated below the minimum guaranteed sampling rate, the T/H droop becomes excessive. This is first observed as an increase in offset voltage, followed by degraded linearity at even lower frequencies. Lower effective sampling rates may be easily supported by operating the converter in Dual Port output mode and using only one output channel. A majority of the power dissipated by the AD9483 is static (not related to conversion rate), so the penalty for clocking at twice the desired rate is not high.
Digital Inputs
SNR performance is directly related to the sampling clock stability in A/D converters, particularly for high input frequencies and wide bandwidths. ENCODE and Data Select (DS) can be driven differentially or single-ended. For single-ended operation, the complement inputs (ENCODE, DS) are internally biased to VDD/3 (~1.5 V) by a high impedance on-chip resistor divider (Figure 5), but they may be externally driven to establish an alternate threshold if desired. A 0.1 F decoupling capacitor to ground is sufficient to maintain a threshold appropriate for TTL or CMOS logic. When driven differentially, ENCODE and DS will accommodate differential signals centered between 1.5 V and 4.5 V with a total differential swing 800 mV (VID 400 mV). Note the 6-diode clock input protection circuitry in Figure 5. This limits the differential input voltage to 2.1 V. When the diodes turn on, current is limited by the 300 series resistor. Exceeding 2.1 V across the differential inputs will have no impact on the performance of the converter, but be aware of the clock signal distortion that may be produced by the nonlinear impedance at the converter.
DRIVING DIFFERENTIAL INPUTS DIFFERENTIALLY CLOCK ENC VIH D VIC M CLOCK ENC VIL D VID
The high bandwidth and low power of the AD9483 makes it very attractive for applications that require the digitization of presampled waveforms, wherein the input signal rapidly slews from one level to another, then is relatively stable for a period of time. Examples of these include digitizing the output of computer graphic display systems, and very high speed solid state imagers. These applications require the converter to process inputs with frequency components well in excess of the sampling rate (often with subnanosecond rise times), after which the A/D must settle and sample the input in well under one pixel time. The architecture of the AD9483 is vastly superior to older flash architectures, which not only exhibit excessive input capacitance (which is very hard to drive), but can make major errors when fed a very rapidly slewing signal. The AD9483's extremely wide bandwidth Track/Hold circuit processes these signals without difficulty.
Using the AD9483
Good high speed design practices must be followed when using the AD9483. Decoupling capacitors should be physically as close as possible to the chip to obtain maximum benefit. We recommend placing a 0.1 F capacitor at each power ground pin pair (14 total) for high frequency decoupling and including one 10 F capacitor for local low frequency decoupling. Each of the three VREF IN pins should also be decoupled by a 0.1 F capacitor. The part should be located on a solid ground plane and output trace lengths should be short (<1 inch) to minimize transmission line effects. This will avoid the need for termination resistors on the output bus and reduces the load capacitance that REV. A -13-
DRIVING DIFFERENTIAL INPUTS SINGLE-ENDEDLY CLOCK ENC VIN D VID VIC M 0.1 F ENC VIL D
Figure 34. Input Signal Level Definitions
AD9483
ADC Gain Control Modes of Operation
Each of the three ADC channels has independent limited gain control. The full-scale signal amplitude for a given ADC is set by the dc voltage on its VREF In pin. The equation relating the full scale amplitude to VREF In is as follows: FS = (0.4) x (VREF IN). The three ADCs are optimized for a full-scale signal amplitude of 1 V, but will accommodate up to 10% variation.
ADC Offset Control
The AD9483 has three modes of operation, Single Channel output mode, and a Dual Channel output mode with two possible data formats, interleaved or parallel. Two pins control which mode of operation the chip is in, Pin 74 Output Mode Select (OMS) and Pin 75 Interleaved/Parallel Select (I/P). Table II shows the configuration required for each mode.
Table II. Output Mode Selection
The offset for each of the three ADCs can be independently controlled. For a single-ended analog input where the analog input is connected to a reference, offset can be adjusted simply by adjusting the dc voltage of the reference. For differential analog inputs, the user must provide the offset in their signal. Offset can be adjusted up or down as far as the common-mode input range will allow.
Power Dissipation
MODE Dual Channel--Parallel Dual Channel--Interleaved Single Channel
Demuxed Output Mode
OMS LOW LOW HIGH
I/P LOW HIGH DON'T CARE
Power dissipation for the AD9483 has two components, VCC and VDD. Power dissipation from VCC is relatively constant for a given supply voltage, whereas power dissipation from VDD can vary greatly. VCC supplies power to the analog circuity. VDD supplies power to the digital outputs and can be approximated by the following equation: P (VDD) = 1/2 C x V 2 x F x N C V F N = = = = Output Load Capacitance VDD Supply Voltage Encode Frequency Number of Outputs Switching
In demuxed mode, (Pin 74 OMS = LOW), the ADC output data are alternated between the two output ports (Port A and Port B). This limits the data output rate to 1/2 the rate of ENCODE, and facilitates conversion rates up to 140 MSPS. Demuxed output mode is recommended for guaranteed operation above 100 MSPS, but may be enabled at any specified conversion rate. Two data formats are possible in Dual Channel output mode, parallel data out and interleaved data out. Pin 75 I/P should be LOW for parallel format and HIGH for interleaved format. Figures 1 and 2 show the timing requirements for each format. Note that the Data Sync input, (DS), is required in Dual Channel output mode for both formats. The section on Data Sync describes the requirements of the Data Sync input. As shown in Figures 1 and 2, when using the interleaved data format, a sample is taken on an ENCODE rising edge N. The resulting data is produced on an output port following the fifth rising edge of ENCODE after the sample was taken, (five pipeline delays). The following sample, (N+1), will be produced on the opposite port, also five pipeline delays after it was taken. The state of CLKOUT when the sample was taken will determine out of which port the data will come. If CLKOUT was LOW, the data will come out Port A. If CLKOUT was HIGH, the data will come out Port B. In order to achieve parallel data format on the two output data ports, the data is internally aligned. This is accomplished by adding an extra pipeline delay to just the A Data Port. Thus, data coming out Port A will have six pipeline delays and data coming out Port B will have five pipeline delays. As with the interleaved format, the state of Data Sync when a sample is taken will determine out of which port the data will come. If CLKOUT was LOW, the data will come out Port A. If CLKOUT was HIGH, the data will come out Port B.
Nominally, C = 10 pF, V = 3.3 V, F = 140 MSPS, and N = 26. N comes from the 24 output bits plus two clock outputs, P(VDD) = 197 mW.
Power-Down
The power-down function allows users to reduce power dissipation when output data is not required. A TTL/CMOS HIGH signal on pin 76, (PD), shuts down most of the chip and brings the total power dissipation to less than 100 mW. The internal bandgap voltage reference remains active during power-down mode to minimize reactivation time. If the power-down function is not desired, the PD pin should be tied to ground or held to a TTL/CMOS LOW level.
Bandgap Voltage Reference
The AD9483 internal reference, VREF OUT (Pin 97), provides a simple, cost effective reference for many applications. It exhibits reasonable accuracy and excellent stability over power supply and temperature variations. The reference output can be used to set the three ADCs' gain and offset. The reference is capable of providing up to 1 mA of additional current beyond the requirements of the AD9483. As the ADC gain and offset are set by the reference inputs, some applications may require a reference with greater accuracy or temperature performance. In these cases, an external reference may be connected directly to the VREF IN pins. VREF OUT, if unused, should be left floating. Note, each of the three VREF IN pins will require up to 1 mA of current.
-14-
REV. A
AD9483
Data Sync
The Data Sync input, DS, is required to be driven for most applications to guarantee at which output port a given sample will appear. When DS is held high, the ADC data outputs and clock outputs do not switch--they are held static. Synchronization is accomplished by the assertion (falling edge) of DS, within the timing constraints TSDS and THDS relative to an encode rising edge. (On initial synchronization THDS is not relevant.) If DS falls TSDS before a given encode rising edge N, the analog value at that point in time will be digitized and available at Port A five cycles later (interleaved mode). The very next sample, N+l, will be sampled by the next rising encode edge and available at Port B five cycles after that encode edge (interleaved mode). In dual parallel mode the A port has a six cycle latency, the B port has a five cycle latency as described in Demuxed Outputs Mode section. DS can be asserted once per video line if desired by using the horizontal sync signal (HSYNC). The start of HSYNC should occur after the end of active video by at least the chip latency. The HSYNC front porch is usually much greater than this in a typical SXGA system. If this is true in a given system then DS can be reset high by the HSYNC leading edge (the samples at that point should not be required in a typical system). DS can then be reasserted (brought low), by triggering from HSYNC trailing edge--observing TSDS of the next rising encode edge. The first pixel data (on A Port) would be available five cycles after the first rising encode after HSYNC goes high. It is possible to use the phase of the data clock outputs and software programming to accommodate situations where DS is not driven. The data clock outputs (CLKOUT and CLKOUT) can be used to determine when data is valid on the output ports. In these cases DS should be grounded and DS left floating or connected to VCC. If CLKOUT was low when a given sample was taken, the digitized value will be available on Port A, five cycles later. Data Sync has no effect when Single Channel Mode is selected, it should be grounded Figure 2 shows how to use DS properly. The DS rising edge does not have any special timing requirements except that no data will come out of either port while it is held HIGH. The falling edge of DS must, however, meet a minimum setup-andhold time with respect to the rising edge of ENCODE.
Single Channel Outputs Mode
The maximum conversion rate in the mode should be limited to 100 MSPS. This is recommended because the guaranteed output data valid time minus the propagation delay is only 4 ns at 100 MSPS. This is about as fast as standard logic is able to capture the data with reasonable design margins. The AD9483 will operate faster in this mode if the user is able to capture the data. When operating in single channel mode, all data comes out the A Ports while the B Ports are held static in a random state.
Data Clock Outputs
The data clock outputs will switch at two potential frequencies. In Single Channel mode, where all data comes out of Port A at the full ENCODE rate, the data clock outputs switch at the same frequency as the ENCODE. In Dual Channel mode, where the data alternates between the two ports, each of which operate at 1/2 the full ENCODE rate, the data clock outputs also switch at 1/2 the full ENCODE rate. The data clock outputs have two potential purposes. The first is to act as a latch signal for capturing output data. In order to do this, simply drive the data latches with the appropriate data clock output. The second use is in Dual Channel data mode to help determine out of which data port data will come out. Refer to Figure 2 for a complete timing diagram, but in this mode, a rising edge on data clock will correspond to data switching on data Port B.
LAYOUT AND BYPASSING CONSIDERATIONS
Proper high speed layout and bypassing techniques should be used with the AD9483. Each VCC and VDD power pin should be bypassed as close to the pin as possible with a 0.01 F to 0.1 F capacitor Also, one 10 F capacitor to ground should be used per supply per board. The VREF OUT pin and each of the three VREF IN pins should also be bypassed with a 0.01 F to 0.1 F capacitor to ground. A single, substantial, low impedance ground plane should be place under and around the AD9483. Try to maximize the distance between the sensitive analog signals, (AIN, VREF), and the digital signals. Capacitive loading on the digital outputs should be kept to a minimum. This can be facilitated by keeping the traces short and in the case of the clock outputs by driving as few other devices as possible. Socketing the AD9483 should also be avoided. Try to match trace lengths of similar signals to avoid mismatches in propagation delays, (the encode inputs, analog inputs, digital outputs).
POWER SUPPLIES
In Single Channel mode, (Pin 74 OMS = HIGH), the timing of the AD9483 is similar to any high speed ADC (Figure 1). A sample is taken on every rising edge of ENCODE, and the resulting data is produced on the output pins following the fourth rising edge of ENCODE after the sample was taken, (four pipeline delays). The output data are valid tPD after the rising edge of ENCODE, and remain valid until at least tV after the next rising edge of ENCODE.
At power up, VCC must come up before VDD. VCC is considered the converter supply, nominally 5.0 V ( 5.0%) VDD is consider output power supply, nominally 3.3 V ( 10%) or 5.0 V ( 5%). At power off, VDD must turn off first. Failure to observe the correct power supply sequencing many damage this device.
REV. A
-15-
AD9483
EVALUATION BOARD Voltage Reference
The AD9483 evaluation board offers an easy way to test the AD9483. It provides ac or dc biasing for the analog input, it generates the output latch clocks for Single Mode, Dual Parallel Mode and Dual Interleaved Mode. Each of the three channels has a reconstruction DAC (A Port only). The board has several different modes of operation, and is shipped in the following configuration: * Single-ended ac coupled analog input (1 V p-p centered at ground) * Differential clock inputs (PECL) (See ENCODE section for TTL drive) * Internal voltage references connected to externally buffered on-chip reference (VREF OUT) * Preset for Dual Mode Interleaved
Analog Input
The AD9483 has an internal 2.5 V voltage reference (VREF OUT). This is buffered externally on board to support additional level shifting circuitry (the AD9483 VREF OUT pin can drive the three VREF IN pins in applications where level shifting is not required with no additional buffering). An external reference may be employed instead to drive each VREF IN pin independently (requires moving Jumpers W14, W15 and W16).
Single Channel Mode
Single Channel mode sets the AD9483 to produce data on every clock cycle on output port A only. The maximum speed in Single Channel mode is 100 MSPS.
Dual Channel Modes (Outputs Clocked at 1/2 Encode Clock) Dual Channel Interleaved
Sets the ADC to produce data alternately on Port A and Port B. the maximum speed in this mode is 140 MSPS.
Dual Channel Parallel
The evaluation board accepts a 1 V p-p input signal centered at ground for ac coupled input mode (Set Jumpers W4, W5, W12, W13, W18, W17 to jump Pin 1 to Pin 2). This signal biased up to 2.5 V by the on-chip reference. Note: input signal should be bandlimited (filtered) prior to sampling to avoid aliasing. The analog inputs are terminated to ground by a 75 resistor on the board. The analog inputs are ac coupled through 0.1 F caps C2, C4, C6 on top of the board. These can be increased to accommodate lower frequency inputs if desired using test points PR1-PR6 on bottom of board. In dc coupled input mode (Set Jumpers W4, W5, W12, W13, W18, W17 to jump Pin 3 to Pin 2 ) the board accepts typical video level signal levels (0 mV to 700 mV) the signal is level shifted and amplified to 1 V p-p by the AD8055 preamp. Trimpots R98-R100 are used to adjust dc black level to 2 V at ADC inputs.
Encode
Sets the ADC to produce data concurrently on Port A and Port B. Maximum speed in this mode is 140 MSPS.
DAC Out
The DAC output is a representation of the data on output Port A only. The DAC is terminated on the board into 75 . Fullscale voltage swing at DAC output is nominally 0 mV to 800 mV when terminated into external 75 (doubly terminated). Output Port B is not reconstructed. The DAC outputs are NOT filtered and will exhibit sampling noise. The DACs can be powered down at W1, W2, and W3 (jumper not installed).
Data Ready
An output clock for latching the ADC outputs is available at Pin 1 at the 25-pin connector. Its complement is located at Pin 14. The clocks are terminated on the board by a 75 Thevenin termination to VD/2. The timing on these clock outputs can be inverted at W9, W10 (jumper not installed).
Schematics
The AD9483 ENCODE input can be driven two ways. 1. Differential PECL (VLO = 3, VHI = 4 nominal). It is shipped in this mode. 2. Single ended TTL or CMOS. (At Encode Bar-Remove 50 termination resistor R10, add 0.1 F capacitor C7)
The schematics for the evaluation board follow. (Note bypass capacitors for ADC are shown in Figure 39.)
Table III. Evaluation Board Jumper Settings
MODE Dual Channel/PARALLEL Dual Channel/INTERLEAVED SINGLE
W7 (OMS) LOW LOW HIGH
W6 (I/P) LOW HIGH DON'T CARE
W11 (A_LAT) DATA_CLK_OUT (4-5) DATA_CLK_OUT (5-6) DATA_CLK_OUT (5-6)
W11 (B_LAT) DATA_CLK_OUT (2-3) DATA_CLK_OUT (2-3) NC
DESIGN NOTES Maximum frequency for PARALLEL is 140 MHz. Maximum frequency for INTERLEAVED is 140 MHz. Maximum frequency for SINGLE is 100 MHz. DS is tied to ground through a 50 resistor. DS is left floating.
-16-
REV. A
AD9483
OUTB A[0-7] 49 OUTB A0 48 OUTB A1 47 OUTB A2 46 OUTB A3 45 OUTB A4 44 OUTB A5 43 OUTB A6 42 OUTB A7 OUTB B[0-7] 39 OUTB A0 38 OUTB A1 37 OUTB A2
36 OUTB A3
35 OUTB A4
34 OUTB A5
33 OUTB A6
OUTA_A[0-7]
OUTA_B[0-7]
32 OUTB A7
OUTC_A[0-7]
OUTC A0 OUTC A1 OUTC A2 OUTC A3 OUTC A4 OUTC A5 OUTC A6 OUTC_A7 OUTC B0 OUTC B1 OUTC B2 OUTC B3 29 OUTC A0 28 OUTC A1 27 OUTC A2 26 OUTC A3 25 OUTC A4 24 OUTC A5 23 OUTC A6 22 OUTC A7 19 OUTC B0 18 OUTC B1 17 OUTC B2 16 OUTC B3 15 OUTC B4 14 OUTC B5 13 OUTC B6 12 OUTC B7 9 8 5 4 3 2 R9 50 OUTC B4 OUTC B5 OUTC B6 OUTC B7 DS DS ENCODE ENCODE
OUTB A0
OUTB A1
OUTB A2
OUTB A3
OUTB A4
OUTB A5
OUTB A6
OUTB A7
OUTB_B0
OUTB_B1
OUTB_B2
OUTB_B3
OUTB_B4
OUTB_B5
OUTB_B6
OUTA B7 OUTA B6 OUTA B5 OUTA B4 OUTA B3 OUTA B2 OUTA B1 OUTA B0 OUTA A7 OUTA A6 OUTA A5 OUTA A4 OUTA A3 OUTA A2 OUTA A1 OUTA A0 1 W7 3 1 W6 3
52 53 54 55 56 57 58 59 62 63 64 65 66 67 68 69
OUTA B7 OUTA B6 OUTA B5 OUTA B4 OUTA B3 OUTA B2 OUTA B1 OUTA B0 OUTA A7 OUTA A6 OUTA A5 OUTA A4 OUTA A3 OUTA A2 OUTA A1 OUTA A0
AD9483
OUTB_B7
VDD
R101 74 2 100
DATA CLK OUT OMS DATA CLK OUT
DATA CLK OUT DATA_CLK_OUT DS DS R10 50
R102 2 100 75 76
I/P PWR DN
A REF IN
B REF IN
C REF IN
REF OUT
C7 0.1 F
AIN A
AIN B
AIN C
AIN A
AIN B
AIN C
OUTC_B[0-7]
ENCODE
NOT INSTALLED J1 SMB
84
85 A REF
87
88 B REF
90
91 C REF
86 A REF
89 B REF
92
97 SMB
ENCODE
J2 ENC
C REF REF OUT
ENC
A REF C1 0.1 F R4 1k 2 W5 1 3 R103 200 6 R86 360 PR2 C2 0.1 F PR1 7 4 -VA PR4
B REF C3 0.1 F R5 1k 2 W13 1 3 R104 200 6 R89 360 7 4 -VA PR5
C REF C5 0.1 F R6 1k 2 W17 1 3 R105 200 6 R90 360 7 4 -VA
VA
U14 AD8055
2 3
VA
U15 AD8055
2 3
VA
U16 AD8055
2 3
R87 274 1 W4 2 3
TRIM A PR3
C4 0.1 F
R88 274 1 W12 3
TRIM B PR6
C6 0.1 F
R91 274 1 W18 3
TRIM C
R1 75 TP1 J7
2
R2 75 TP3 J6
2
R3 75 J5
TP2 BNC
BNC
BNC
Figure 35. ADC and Preamp Section
REV. A
-17-
AD9483
A_LAT U6 EN C1 GND: 10 VD: 20 C1 C1 19 RED A0 1D 18 RED A1 17 RED A2 16 RED A3 15 RED A4 14 RED A5 13 RED A6 12 RED A7 74LCX574 74LCX574 OUTB A7 9 12 GREEN A7 OUTC A7 9 74LCX574 OUTB A6 8 13 GREEN A6 OUTC A6 8 OUTB A5 7 14 GREEN A5 OUTC A5 7 OUTB A4 6 15 GREEN A4 OUTC A4 6 OUTB A3 5 16 GREEN A3 OUTC A3 5 OUTB A2 4 17 GREEN A2 OUTC A2 4 OUTB A1 3 18 GREEN A1 OUTC A1 3 1D 1D OUTB A0 2 19 GREEN A0 OUTC A0 2 11 GND: 10 VD: 20 GND: 10 VD: 20 19 BLUE A0 18 BLUE A1 17 BLUE A2 16 BLUE A3 15 BLUE A4 14 BLUE A5 13 BLUE A6 12 BLUE A7 11 GND EN EN 1 GND 1 U10 U8 VD R7 301 R8 301
GND
1
11
OUTA A0 2
OUTA A1 3
OUTA A2 4
OUTA A3 5
OUTA A4 6
OUTA A5 7
OUTA A6 8
OUTA A [0-7]
OUTA A7 9
OUTB A [0-7]
OUTC A [0-7]
Figure 36. Output Latches Section
-18-
U9 EN C1 GND: 10 VD: 20 C1 19 RED B0 1D 18 RED B1 17 RED B2 16 RED B3 15 RED B4 14 RED B5 13 RED B6 12 RED B7 74LCX574 OUTB B6 8 OUTB B7 9 74LCX574 OUTB B5 7 OUTB B4 6 OUTB B3 5 OUTB B2 4 OUTB B1 3 1D OUTB B0 2 11 GND: 10 VD: 20 19 GREEN B0 18 GREEN B1 17 GREEN B2 16 GREEN B3 15 GREEN B4 14 GREEN B5 13 GREEN B6 12 GREEN B7 GND EN 1 U7
B_LAT U11 GND 1 11 EN C1 GND: 10 VD: 20 OUTC B0 2 OUTC B1 3 OUTC B2 4 OUTC B3 5 OUTC B4 6 OUTC B5 7 OUTC B6 8 OUTC B7 9 74LCX574 1D 19 BLUE B0 18 BLUE B1 17 BLUE B2 16 BLUE B3 15 BLUE B4 14 BLUE B5 13 BLUE B6 12 BLUE B7 R76 301 R77 301 VD
GND
1
11
OUTA B0 2
OUTA B1 3
OUTA B2 4
OUTA B3 5
OUTA B4 6
OUTA B5 7
OUTA B6 8
OUTA B [0-7]
OUTA B7 9
OUTB B [0-7]
OUTC B [0-7]
REV. A
IO
IO
SLEEP
SLEEP
LO
FSADJ
LO
FSADJ
SLEEP
28 C9 0.1 F W3 R11 1k R12 1k DAC CLK VD C13 0.1 F
15
16
17 18
28
15
16
17 18 DAC CLK VD R23 1k W2
28
15
LO
16
DAC CLK VD
W1
Figure 37. DACs and Clock Buffer Section
R19 1k
R20 1k
IO
17 18 C16 0.1 F
FSADJ
REV. A
R78 0 DR VD : 14 GND : 7 W8 R73 2k VD C12 0.1 F C17 0.1 F 23 23 C15 0.1 F VD R22 2k VD C10 0.1 F C14 0.1 F VD VD : 14 GND : 7 B LAT DR A LAT R79 0 U1 74LCX86 4 6 5 U1 74LCX86 9 8 10 DAC_CLK VD : 14 GND : 7 W10 VD SMB R14 75 J10 U3 19 24 27 2 1 A D DB0 COMP COMP DB1 DB2 22 I OUT A DB3 SMB R16 75 J10
A LAT
U1 74LCX86 1 3 2
W9
R21 2k
VD
C11 0.1 F
19 24 27 U2 2 1 A D COMP DB0 COMP DB1 DB2 22 I OUT A DB3
23
AD9760
I OUT B R24 75 21
AD9760
I OUT B GND: 20,26 CLK REF
RED RED RED RED RED RED RED RED REF
A0 A1 A2 A3 A4 A5 A6 A7 GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN
10 9 8 7 6 5 4 3 2 1 A0 A1 A2 A3 A4 A5 A6 A7 10 9 8 7 6 5 4 3 2 1 BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE A0 A1 A2 A3 A4 A5 A6 A7
DB4 DB5 DB6 DB7 DB8 DB9
GND: 20,26
10 9 8 7 6 5 4 3 2 1
-19-
VD R80 150 DR R61 150 R62 150 DR R83 150 VD
DB4 DB5 DB6 DB7 DB8 DB9
21 R15 75
CLK
U4 19 24 27 2 1 A D COMP DB0 COMP DB1 SMB DB2 22 I OUT A DB3 J5 R18 DB4 75 AD9760 DB5 DB6 DB7 21 DB8 I OUT B GND: 20,26 R17 DB9 75 REF CLK
R13 1k
CLOCK LINE TERMINATIONS
VD
R85 150
DAC CLK
R64 150
AD9483
RED_A0 R44 100 R46 100 R47 100 R48 100 R43 100 R42 100 R41 100 GR_A7 NOT INSTALLED GR_B0 DR U1 74LCX86 12 GR_B3 13 GR_B4 VD: 14 GND: 7 EXTRA GATES GR_B5 GR_B6 GR_B7 11 DR GR_B1 GR_B2 C8 0.1 F R75 50 R52 100 R53 100 R51 100 R50 100 R49 100 R54 100 R55 100 R56 100 GR_A6 J3 DS GR_A5 SMB GR_A4 GR_A3 R74 50 DS J4 GR_A2 SMB GR_A1
R26 100 GR_A0
R_A0
GREEN_A0
R45 100
AD9483
RED_A1
R25 100
RED_A2
R27 100
R_A1
GREEN_A1
RED_A3
R28 100
R_A2
GREEN_A2
RED_A4
R29 100
R_A3
GREEN_A3
RED_A5
R30 100
R_A4
GREEN_A4
RED_A6
R31 100
R_A5
GREEN_A5
RED_A7
R32 100
R_A6
GREEN_A6
R_A7
GREEN_A7
DR GND R_A0 R_A1 R_A2 R_A3 R_A4 R_A5 R_A6 R_A7 GND
DR GND GR_A0 GR_A1 GR_A2 GR_A3 GR_A4 GR_A5 GR_A6 GR_A7 GND
DR GND BL_A0 BL_A1 BL_A2 BL_A3 BL_A4 BL_A5 BL_A6 BL_A7 GND
RED_B0
R68 100
R_B0
GREEN_B0
RED_B1
R69 100
DR
RED_B2
R67 100
R_B1
GREEN_B1
RED_B3
R66 100
R_B2
GREEN_B2
RED_B4
R65 100
R_B3
GREEN_B3
RED_B5
R70 100
R_B4
GREEN_B4
RED_B6
R71 100
R_B5
GREEN_B5
Figure 38. Digital Outputs Connectors and Terminations Section
GND R_B0 R_B1 R_B2 R_B3 R_B4 R_B5 R_B6 R_B7 GND GND GR_B0 GR_B1 GR_B2 GR_B3 GR_B4 GR_B5 GR_B6 GR_B7 GND CUSTOMER WORKSPACE CON-DB25HF P1 CON-DB25HF P2 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 ST1 U13 ST4 U13 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 ST4 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 20 1 19 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 10 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 ST1 20 1 19 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 10 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 P1 P2 P3 P4 P5 ST8 GND ST7 1 2 3 4 5 P1 P2 P3 P4 P5 1 2 3 4 5 P1 P2 P3 P4 P5 ST5 1 2 3 4 5 1 2 3 4 5 P1 P2 P3 P4 P5 ST6 VD
-20-
RED_B7
R72 100
R_B6
GREEN_B6
R_B7
GREEN_B7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 GND BL_B0 BL_B1 BL_B2 BL_B3 BL_B4 BL_B5 BL_B6 BL_B7 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
BLUE_A0
R36 100
BL_A0
BLUE_A1
R37 100
BL_A1
CON-DB25HF P3
BLUE_A2
R35 100
BLUE_A3
R34 100
BL_A2
BLUE_A4
R33 100
BL_A3
BLUE_A5
R38 100
BL_A4
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10
BLUE_A6
R39 100
BL_A5
BLUE_A7
R40 100
BL_A6
BL_A7
TEST POINT GROUNDS
BLUE_B0
R61 100
BL_B0
BLUE_B1
R60 100
BLUE_B2
R62 100
BL_B1
BLUE_B3
R63 100
BL_B2
BLUE_B4
R64 100
BL_B3
BLUE_B5
R59 100
BL_B4
BL_B5
BLUE_B6
R58 100
BL_B6
REV. A
BLUE_B7
R57 100
BL_B7
REV. A
VA C20 0.1 F C50 0.1 F C19 0.1 F C57 0.1 F C23 0.1 F C21 0.1 F C22 0.1 F C24 0.1 F C25 0.1 F C26 0.1 F C55 10 F BYPASS CAPS VD C52 10 F C27 0.1 F C28 0.1 F C29 0.1 F C30 0.1 F C31 0.1 F C32 0.1 F C33 0.1 F C34 0.1 F C63 10 F C60 0.1 F C61 0.1 F C62 0.1 F C65 0.1 F -VA C18 10 F C35 0.1 F C49 0.1 F C36 0.1 F C37 0.1 F C38 0.1 F C39 0.1 F C40 0.1 F C42 0.1 F C43 0.1 F C44 0.1 F C45 0.1 F C56 10 F VD REF SOURCE SELECT A REF R92 1.3k C46 0.1 F R96 1.3k C47 0.1 F R95 1.3k C48 0.1 F R94 1.5k R99 500 TRIM C C REF R97 1.5k R100 500 B REF 1 TRIM B 2 3 6 5 4 A_LAT R98 500 R93 1.5k TRIM A LATCH CLK SOURCE SELECT W11 DATA_LOCK_OUT W14 1 2 3 W15 1 2 3 W16 1 2 3 DATA_LOCK_OUT B_LAT
POWER/DC INPUTS
TB1
1
-VA AD9483 SUPPORT LOGIC - SUPPLY
2
VA AD9483 ANALOG SUPPLY
3
-VA AD9483 DIGITAL SUPPLY
4
-VA AD9483 SUPPORT LOGIC + SUPPLY
5
EXT REF A
6
EXT REF B
7
AD9483 EXTERNAL REFERENCES
EXT REF C
8
GND
VA
2
7
Figure 39. Power Connector, Decoupling Capacitors, DC Adjust Trimpot Section
-21-
AD9483
6
3
4
REF OUT C41 0.1 F
-VA
EXT REF A
C51 10 F
EXT REF B
C53 10 F
EXT REF C
C54 10 F
AD9483
AD9483
PCB LAYOUT Table IV. 25-Pin Connector Pinout
The PCB is designed on a four layer (1 oz. Cu) board. Components and routing are on the top layer with a ground flood for additional isolation. Test and ground points were judiciously placed to facilitate high speed probing. Each channel has a separate 25-pin connector for it's digital outputs. A common ground plane exists on the second layer. The third layer has the 3 split power planes: 1. 5 V analog for the ADC and preamps, 2. 3.3 V (or 5 V) ADC output supply, and 3. A separate 3.3 V supply for support logic. The fourth layer contains the -5 V plane for the preamps and additional components and routing. There is additional space for two extra components on top of the board to allow for modification.
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Pin Name DR (Data Ready) GND A0 A1 A2 A3 A4 A5 A6 A7 GND NC (No Connect) NC (No Connect) DRB (Data Ready Bar) GND B0 B1 B2 B3 B4 B5 B6 B7 GND NC (No Connect)
-22-
REV. A
AD9483
Figure 40. Layer 1. Routing and Top Layer Ground
Figure 41. Layer 2 Ground Plane
REV. A
-23-
AD9483
Figure 42. Layer 3 Split Power Planes
Figure 43. Layer 4 Routing and Negative 5 V
-24-
REV. A
AD9483
EVALUATION BOARD PARTS LIST
# 1 2 3
QTY REFDES 54 8 16 C1-17, C19-50, C57, C60-62, C65 C18, C51-56, C63 GND1-10, PR1, PR2, PR3, PR4, PR5, PR6 J1-4, J8-10 J5-7 P1-3 R1-3, R14-18, R24 R4-6, R11-13, R19-20, R23 R7-8, R76-77 R9-10, R74-75 R21-22, R73 R25-72, R101-102 R78-79 R80-85 R86, R89-90 R87-88, R91 R92, R95-96 R93-94, R97 R98-100 R103-105 ST1-4 ST5-8 TB1
DEVICE CAPACITOR CAPACITOR PART OF PCB
PACKAGE 0805 TAJD OMIT
PART NUMBER C0805C104K5RAC7025 T491C106K016AS
VALUE 0.1 F 10 F
SUPPLIER KEMIT KEMIT
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
7 3 3 9 9 4 4 3 50 2 6 3 3 3 3 3 2 4 4 1
CONNECTOR CONNECTOR CONNECTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR TRIMMER RESISTOR PART OF PCB PART OF PCB POWER CONNECTOR (2 PIECE) PART OF PCB MC74LCX86D AD9760AR AD9483KS-140/100 MC74LCX574DW AD8055AN DIP20 2 PIN JUMPER 3 PIN JUMPER 6 PIN JUMPER SJ-5518
SMB BNC "D" 25 PINS 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206 VRES 1206 STRIP10 STRIP5 TB8A TSTPT SO14NB SO28WB MQFP-100 SO20WB SO8NB DIP20 JMP-2P JMP-3P JMP_6
B51-351-000-220 227699-2 745783-2 CRCW120675R0FT CRCW12061001FT CRCW12063010FT CRCW120649R9FT CRCW12062001FT CRCW12061000FT CRCW1206000ZT CRCW12061500FT CRCW12063600FT CRCW12062740FT CRCW12061301FT CRCW12061501FT 3296W001501 CRCW12062000F NOT INSTALLED NOT INSTALLED 95F6002 50F3583 NOT INSTALLED MC74LCX86D AD9760AR AD9483KS-140/100 MC74LCX574DW AD8055AN NOT INSTALLED SEE NOTE SEE NOTE SEE NOTE 75 1K 301 49.9 2K 100 0 150 360 274 1.3K 1.5K 500 200
ITT CANNON AMP AMP DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE BOURNES DALE
WIELAND
24 25 26 27 28 29 30 31 32 33 34
3 1 3 1 6 4 2 6 11 1 5
TP1-3 U1 U2-4 U5 U6-11 U12, U14-16 U13, U17 W1-3, W8-10 W4-7, W12-18 W11 FEET
MOTOROLA ADI ADI MOTOROLA ADI
3M
NOTES All resistors are surface mount (size 1206) and have a 1% tolerance. Jumpers are Samtec parts TSW-110-08-G-D and TSW-110-08-G-S. Jumpers W1, W2, W3, W9, W8, W10 are omitted.
REV. A
-25-
AD9483
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
100-Lead Plastic Quad Flatpack (S-100B)
0.921 (23.4) 0.906 (23.0) 0.791 (20.10) 0.783 (19.90) 0.742 (18.85) TYP
80 81 51 50 51 50
CONDUCTIVE HEAT SINK ON BOTTOM OF PACKAGE
80 81
0.486 (12.35) TYP
TOP VIEW
(PINS DOWN)
0.555 (14.10) 0.547 (13.90) 0.685 (17.4) 0.669 (17.0)
BOTTOM VIEW
(PINS UP)
0.362 (9.2)
0.551 (14.0)
PIN 1 100 1 31 30 31 30
0.433 (11.0)
100 1 PIN 1
0.029 (0.73) 0.023 (0.57) 0.134 (3.40) MAX 0.041 (1.03) 0.031 (0.78) SEATING PLANE
0.015 (0.35) 0.009 (0.25) 0.110 (2.80) 0.102 (2.60) 0.004 0.010 (0.10) (0.25) MAX MIN
0.787 (20.0)
NOTE: THE AD9483KS PACKAGE USES A COPPER INSERT TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OVER THE FULL 0 C TO +85 C TEMPERATURE RANGE. THIS COPPER INSERT IS EXPOSED ON THE UNDERSIDE OF THE DEVICE. IT IS RECOMMENDED THAT DURING THE DESIGN OF THE PC BOARD NO THROUGHHOLES OR SIGNAL TRACES BE PLACED UNDER THE AD9483 THAT COULD COME IN CONTACT WITH THE COPPER INSERT. COMMONLY ACCEPTED BOARD LAYOUT PRACTICES FOR HIGH SPEED CONVERTERS SPECIFY THAT ONLY GROUND PLANES SHALL BE LOCATED UNDER THESE DEVICES TO MINIMIZE NOISE OR DISTORTION OF VIDEO SIGNALS.
-26-
REV. A
PRINTED IN U.S.A.
C3268a-1-12/98

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